Oftentimes in Verilog code, we build testbenches (test fixtures). A common thing to do is to instantiate a module and plug in wires of the same names.
Now a common hack is to copy and paste the module declaration line (the “prototype,” if you will). The prototype looks like this:
module Foo( bar,
The HDL synthesizer can correctly wire inputs, regardless of instantiated order, by surrounding the names of the local wires with the input names as declared in the prototype in a format such as:
Foo foo_instance ( .bar(bar),
So to do so is a rather painful matter of adding a period before the input name, copy and pasting the input name and pasting it after the name, bracketed by parentheses.
But what do you do if your module has thirty inputs? Our previous solution was to surrender our wrists to inevitable Repetitive Stress Injuries. Today, I realized that I should have used a freakin’ elementary regular expression.
Wah-lah! I’m kicking myself for not thinking of this earlier. And it has taken me 10 minutes to tell you how I saved forty-five seconds and my poor wrists. Anything to avoid more work (shh, don’t tell Alex) :)